Semiconductor Engineering

IEEE 1076.4-VHDL Synthesis Package – Floating Point

The goal of VITAL (VHDL Initiative Towards ASIC Libraries) was to accelerate the development of sign-off quality ASIC macro-cell simulation libraries written in VHDL by leveraging existing ...
Business Wire

Aldec and SynthWorks Deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the ...
Semiconductor Engineering

IEEE 1076.1.1-VHDL-AMS Standard Packages

Work started on the multiple energy domain packages in 2001 with the IEEE group being officially formed in May 2002. The committee approved it in 2004 and created an updated version in 2011. This ...
Design-Reuse

Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM

Henderson, NV – January 9, 2012 – Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), ...
elEconomista

Aldec and SynthWorks Deliver Randomization and Functional CoverageCapabilities to VHDL Designers with OS-VVM TM

Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM TM), underscoring the partnership´s commitment to ...