EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
Electronic Design

Measuring Stability in Modern Clock and Timing Systems

Already registered? Click here to login now! Attend live for a chance to win a Moku:Go! Clock and timing performance plays a critical role in modern RF, analog, and mixed-signal systems, impacting ...
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application (.PDF download)

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...