Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...
CNET

AMD's SSE5 ends the old RISC vs. CISC debate

Prompted by the chipmaker's announcement of the SSE5 instruction-set extensions, Glaskowsky analyzes the ultimate outcome to this old controversy. Peter N. Glaskowsky is a computer architect in ...
ExtremeTech

RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source

A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor -- and to do so with an architecture that's fundamentally open and available to ...
Semiconductor Engineering

How To Extend The ‘Unscalable’ RISC Architectures

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable. This blog was really quite interesting and made some very ...
Ars Technica

AMD chips RISC or CISC?

I was just wanting to know if anyone can tell me if the new athlon mp and xp's are risc chips or if they went to cisc. I know the older AMD chips were all RISC, but not sure of the newer ones. When ...
EDN

MemoryLogix IP core combines CISC and RISC

SAN JOSE–Looking to alter the embedded chip landscape, startup MemoryLogix Inc. took the Microprocessor Forum last week to unveil the company and disclose the development of a “586-based ...
ZDNet

RISC-V opens up processor design

Today, if you want to build a high-performance computing device, you can almost certainly find all the software you need in a free and open form. The same is not true for the processor chips that run ...