EDN

Understanding the basics of PLL frequency synthesis

Configuring a phase locked loop (PLL) for a given frequency synthesis application can simultaneously be both a quick-and easy-process as well as a time-consuming, tedious, and iterative process. This ...
EDN

The CS4350 PLL DAC Simplifies System Design

Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and modulators, as well as some portions of their discrete time analog circuitry. This ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
Design-Reuse

Tutorial on PLLs: Part 1

Few topics in electrical engineering have demanded as much attention over the years as the phase-locked loop (PLL). The PLL is arguably one of the most important building blocks necessary for modern ...
Design-Reuse

Specifying a PLL Part 2: Jitter Basics

No real clock sources (PLL’s, DLL’s, Crystal Oscillators, even function generators) exist that have a single, fixed value for their output period. The output period of all real clock sources changes ...