Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.

This application note presents the simultaneous clock-synchronous serial data transmission and reception. It presents the specifications, the functions used, principles of operation and the ...

Digital Core Design, the Poland-based IP core design house, has developed the DSPI_FIFO, a fully configurable SPI master/slave device, which allows the SoC designer to configure polarity and phase of ...

Serial buses dot the landscape of embedded design. From displays to storage to peripherals, serial interfaces make communications possible. Many serial communication interfaces compete for use in ...

I know you’ve heard of both synchronous and asynchronous communications. But do you really know the differences between the two? Serial communication was used long before computers existed. A ...

Sorry, sidetracked again! But we’re here now! And we’ve got a great little product to tell you about: a clock designed to help procrastinators — well okay ...

The company's second-generation family of PCI Express clock buffers provides reference clocks for serial connectivity at 5 Gb/s and meets the reference clock requirements of fully buffered DIMMs. The ...

I2C is a two-wire, bidirectional bus protocol that enables effective communication between one master (or multiple masters) and one or more slave devices. It is a straightforward, half-Duplex, ...

The MAX3950 is designed to convert 10-Gbps serial data to 16-bit-wide, 622-Mbps parallel data. Its ability to handle FEC data rates make the MAX3950 ideal for a variety of applications in SDH/SONET ...