AOL

Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC's CoWoS™ Referenc

WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corp. (NAS: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC's new ...
AOL

Mentor Graphics Design and Verification Tools Certified for TSMC 16nm FinFET

WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corp. (NAS: MENT) today announced that its Calibre® physical verification platform has achieved version 0.1 of design reference manual (DRM) and ...
Business Wire

Mentor Graphics Provides Design, Verification and Test Solutions for TSMC’s 20nm Design Infrastructure

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corp. (NASDAQ: MENT) today announced new capabilities to complement TSMC’s 20nm manufacturing processes. Enhancements to support both digital and ...
Design-Reuse

Mentor Graphics, Northwest Logic, and Krivi Semiconductor Announce Availability of Complete DDR4 SDRAM IP Design and Verification Solution

WILSONVILLE, Ore, Oct. 05, 2016 – Mentor Graphics ® Corporation (MENT), Northwest Logic and Krivi Semiconductor today announced the availability of a complete DDR4 SDRAM IP design and verification ...
EDN

Mentor Graphics : Breakthrough in verification intelligence improves verification coverage

Mentor Graphics Corp. has announced the Questa® Multi-view Verification Components product and the inFact™ intelligent testbench automation tool – two new solutions that use breakthrough technologies ...
Design-Reuse

Mentor Graphics Teams with Infineon to Deploy State-of-the-Art Verification

WILSONVILLE, Ore., December 1, 2010-Mentor Graphics Corporation (NASDAQ: MENT) today announced it has successfully supported Infineon to improve Infineon's verification productivity and effectiveness ...
Electronic Design

Cadence, Mentor Graphics agree on SystemVerilog verification

Cadence Design Systems (www.cadence.com) and Mentor Graphics (www.mentor.com) have agreed to standardize on an open source methodology for verifying SystemVerilog design files. Cadence Design Systems ...
EDN

Mentor Graphics Drives Next-Generation, Low-Power Verification with UPF Successive Refinement Methodology

The Unified Power Format (UPF) Successive Refinement Methodology enables the incremental specification and early verification of power management intent. The Questa ® Power Aware Simulation solution ...
Nasdaq

Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs

VC Formal Datapath Validation application delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques The new app ...
Semiconductor Engineering

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted ...
Digi Times

TSMC collaborates with Mentor Graphics enabling design and verification tools for new InFO technology variants

TSMC has extended its collaboration with Mentor Graphics on the Xpedition Enterprise platform in conjunction with the Calibre platform for the design and verification of TSMC's integrated fan-out ...