EDN

Metastability and Clock Uncertainty in FPGA Designs

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...
EDN

Design clock controllers for hierarchical test

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation ...
Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Semiconductor Engineering

Verification Of Multi-Clock Designs: The Bigger Picture

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this ...
autoevolution

MTR Designs’ Ferrofluid Clock Will Bring a Touch of Awesome Into Your Office

If you’re into science and neat gadgets, maybe the Ferrofluid Clock from MTR Designs is the thing for you, as it manages to combine both into an elegant and unique timepiece that’s bound to become the ...